IEEE CAS DLP and VLSI/CAD Workshop
IEEE CAS DLP and VLSI/CAD Workshop
中華民國九十七年九月十日星期三
國立清華大學資訊電機館地下一樓演講廳(B01)
主辦單位 : 國立清華大學資訊工程學系 |
報名期限:即日起至97/09/03 |
08:00~08:30 |
Registration |
08:30~09:50 |
Synergistic Modeling and Optimization for Nanometer IC Design/Manufacturing Integration |
09:50~10:20 |
Coffee Break |
10:20~11:40 |
Delay Test Quality for Logic Circuits |
11:40~13:00 |
Lunch |
13:00~14:20 |
Reliable Nanometer IC Design on Top of Unreliable Transistors |
14:20~14:30 |
Break |
14:30~15:50 |
Multi-Scale Thermal Analysis for Nanometer-Scale Integrated Circuits |
15:50~16:00 |
Break |
16:00~17:20 |
New Synthesis and Architecture Solutions for Reconfigurable ICs |
17:20 |
|
David Z. Pan
Department of Electrical and Computer Engineering
The University of Texas at Austin, TX 78712
http://www.cerc.utexas.edu/utda
Nanometer IC design and manufacturing are facing unprecedented grand challenges for 45nm and beyond, according to ITRS. On one hand, many entangled physical effects continue to pose tremendous challenges to reach design closure with stringent turn-around-time; on the other hand, design closure no longer guarantees manufacturing closure. The conventional contracts between design and fab through design rules are breaking, due to deep sub-wavelength lithography and growing process variations. Thus design/manufacturing integration and co-optimization will become more and more important. To enable true design/process integration, it is crucial to be able to model proper manufacturing/variability/yield metrics, and feed them upstream at various physical design implementation stages. This lecture will present synergistic modeling and optimization issues on both physical and electrical design for manufacturing (DFM). We will seek to address DFM from its root causes, in a holistic manner through better manufacturing for design (e.g., variation aware lithography modeling and optical proximity correction), manufacturing-design interface (e.g., predictive silicon modeling and variational circuit analysis), and true “design” for manufacturing (e.g., manufacturability aware routing and variational aware clock synthesis).
David Z. Pan received his Ph.D. in computer science (with honor) from UCLA in 2000. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is an Associate Professor at the Department of Electrical and Computer Engineering, University of Texas at Austin, where he directs the UT Design Automation (UTDA) Lab. His research is mainly focused on nanometer physical CAD and design for manufacturability. He is also interested in design/CAD of emerging technologies. He holds 5 U.S. patents and has published over 80 technical papers. He has served as an Associate Editor for IEEE Transactions on CAD (2006-), IEEE Transactions on VLSI Systems (2007-), IEEE Transactions on CAS-I (2008-), IEEE Transactions on CAS-II (2006-2007), and IEEE CAS Society Newsletter (2007-). He is on the DFM committee of the International Technology Roadmap for Semiconductor (ITRS). He has served in the program committees of major VLSI/CAD conferences including ICCAD, ASPDAC, DATE, ISPD, ISQED, and ISCAS. He is the 2007 IEEE/CANDE Workshop Chair, Program/General Chair for ISPD 2007/2008, CAD Track Co-Chair for ISCAS 2006 and 2007. He has received a number of awards for his research contributions, including the ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Awards (2000 and 2008), IBM Faculty Awards (2004 to 2006), IBM Research Bravo Award (2003), Best Paper Award Nominations at DAC (2006) and ASPDAC (2006 and 2008), ISPD 2007 Global Routing Contest Awards, Best Paper in Session Award at SRC Techcon (1998 and 2007), and ACM Recognition of Service Award (2007). He is a Senior Member of IEEE.
Delay test quality for logic circuits
Prof. Seiji Kajihara
Department of Computer Science and Electronics of Kyushu Institute of Technology
E-mail: kajihara@cse.kyutech.ac.jp
In deep-submicron VLSIs, faults that affect timing behavior of logic circuits more likely occur due to various reasons such as a resistive open/short, circuit noise, or process variation. Even for the increase of small delay, the circuits are often affected. Therefore, conventional stuck-at fault testing is not sufficient and delay testing is becoming more and more important.
In this talk, we introduce recent techniques for delay testing. Especially we focus on the following things:
(1) Test application methods for scan circuits
(2) Evaluation of delay test quality of test patterns for transition faults
(3) ATPG techniques for high delay test quality
Seiji Kajihara received the B.S. and M.S. degrees from Hiroshima University, Japan, and the Ph.D. degree from Osaka University, Japan, in 1987, 1989, and 1992, respectively. From 1992 to 1995, he worked with the Department of Applied Physics, Osaka University, as an Assistant Professor. In 1996, he joined the Department of Computer Science and Electronics of Kyushu Institute of Technology, Japan, where he is a Professor currently. His research interest includes test generation, delay testing, and design for testability. He received the Young Engineer Award from IEICE in 1997, the Yamashita SIG Research Award from IPSJ in 2002, and the Best Paper Award from IEICE in 2005. Dr. Kajihara is a member of the IEEE, and the IPSJ.
Reliable Nanometer IC design on top of Unreliable Transistors
Prof. Yuan Xie
Department of Computer Science and Engineering
Pennsylvania State University
As technology scales, designing a reliable system atop a less reliable hardware platform poses great challenges for designers. The major reliability issues for nanometer IC design include transient errors, aging effect, and process variations. Many techniques to improve reliability can incur performance, energy, or cost penalties. Further, some solutions targeted at a specific failure mechanism could negatively affect other mechanisms. For example, lowering operational voltage can help mitigate aging effects but increases vulnerability to soft errors. Developers must understand the tradeoffs when designing reliable systems. This presentation will first introduce various reliability concerns, including soft errors, aging effect, and process variations, and then discuss analysis and optimization techniques for reliable system design.
Prof. Xie received his B.S. degree from Tsinghua University, and his M.S. and Ph.D. degrees from Electrical Engineering Department, Princeton University. Prior to joining Penn State in Fall 2003, he worked as an Advisory Engineer for IBM Microelectronics Division's Worldwide Design Center. He was a recipient of the NSF CAREER award in 2006. Prof. Xie's research interests include VLSI Design, Electronics Design Automation, Computer Architecture, Embedded Systems Design. Specifically, recent research projects he has been involved include EDA tools and architectures for 3D IC design, embedded system synthesis, low power and thermal-aware techniques, robust design techniques related to soft errors and process variation.
Multi-Scale Thermal Analysis for Nanometer-Scale Integrated Circuits
Li Shang
Electrical and Computer Engineering
University of Colorado at Boulder
Thermal analysis has long been essential for designing reliable, high-performance, cost-effective integrated circuits (ICs). Increasing power densities are making this problem more important. Characterizing the thermal profile of an IC quickly enough to allow feedback on the thermal effects of tentative design changes is a daunting problem, and its complexity is increasing. The move to nanoscale fabrication processes is increasing the importance of quantum thermal phenomena such as ballistic phonon transport. Accurate thermal analysis of nanoscale ICs containing hundreds of millions of devices requires characterization of thermal effects on length scales that vary by several orders of magnitude, from nanoscale quantum thermal effects to centimeter-scale cooling package impact. In this talk, we present ThermalScope, a multi-scale thermal analysis method for nanoscale IC design. It unifies microscopic and macroscopic thermal physics modeling methods, i.e., the Fourier and Boltzmann transport modeling methods. Moreover, it supports adaptive multi-resolution modeling. Together, these ideas enable efficient and accurate characterization of nanoscale quantum heat transport as well as chip--package level heat flow. ThermalScope is designed for full-chip thermal analysis of billion-transistor nanoscale IC designs, with accuracy at the scale of individual devices.
Li Shang received his Ph.D. degree from Princeton University in 2004, and his B.E. degree with honors from Tsinghua University in 1997. Dr. Shang is currently an Assistant Professor at the Department of Electrical and Computer Engineering, University of Colorado at Boulder. Before that, he was with the Department of Electrical and Computer Engineering, Queen's University Canada. His research focuses on design automation, circuit design, computer architecture, and design for nanotechnologies. His recent work was nominated for the Best Paper Award at ICCAD 2008, DAC 2007, and ASP-DAC 2006. His work on temperature-aware on-chip network has been selected for publication in MICRO Top Picks 2006. He also won the Best Paper Award at PDCS 2002. He is currently serving as an Associate Editor of IEEE Transactions on VLSI Systems and ASP journal of low power electronics. He serves on the technical program committees of several VLSI and Embedded Systems conferences. He won his department's Best Teaching Award in 2006. He is the Walter F. Light Scholar
New Synthesis and Architecture Solutions for Reconfigurable ICs
Deming Chen
Department of Electrical and Computer Engineering
University of Illinois, Urbana-Champaign
The semiconductor industry has showcased the spectacular exponential growth of device complexity and performance for four decades, predicted by Moore's Law. Programmable logic devices (PLDs), especially field programmable gate arrays (FPGAs), have grown at an even faster pace than the rest of the semiconductor industry. Currently, both Altera and Xilinx offer FPGAs with hundreds of thousands of logic elements, as well as a large number of hard-wired macro blocks, embedded processors, high-speed IOs, and clock synchronization circuitry. To support the design of such complex programmable devices, computer-aided design (CAD) plays a critical role in delivering high-performance, high-density, and low-power design solutions using these high-end FPGAs. Meanwhile, conventional top-down manufacturing faces increasing challenges due to fundamental physical and economical constraints. In contrast, bottom-up approaches, in which integrated functional device structures are assembled from chemically synthesized nanoscale building blocks, such as carbon nanotubes (CNT) and nanowires, have the potential to revolutionize the fabrications of electronic systems for the future. Such nanosystems are by their nature very regular in structure and therefore suitable to the implementation similar to FPGAs. In this talk, we introduce our recent research results on CAD for conventional FPGAs and architecture design for nanoFPGAs. The first half of the talk touches on new synthesis techniques for FPGAs targeting high performance, low power, and designs with false paths and multi-clock domains. In the second half, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically.
Dr. Deming Chen obtained his BS from University of Pittsburgh, Pennsylvania in 1995 and his PhD from University of California at Los Angeles in 2005 all from the Computer Science department. He worked as a software engineer between 1995-1999 and 2001-2002. He joined the ECE department of UIUC as a faculty member in 2005. He has been actively publishing in high-level and logic synthesis, low power design, FPGA design and synthesis, and design and CAD with nanotechnology in various leading CAD conferences and journals. Several of his publications in FPGA synthesis and power estimation have been widely cited in the research community. Some of his research results represent the state-of-the-art performance- and low power-driven synthesis techniques. His work also optimally solved a series of problems encountered in high-level and logic synthesis. Several of his research ideas have already been incorporated in commercial software that is distributed to many customers of leading companies (e.g., Altera and Magma).
His current research interests include CAD for FPGA, nano-systems design and nano-centric synthesis, microprocessor architecture design under process/parameter variation, and reconfigurable computing. He is a technical committee member for FPGA'06-08, ASPDAC'07-08, ISCAS'07-08, ICCD'07-08, and FPL'08. He is a session chair for ICCD'05, ASPDAC'07, ICCAD'07, and FPGA'08. He is a subcommittee chair for ASPDAC technical committee starting 2009. He obtained the Achievement Award for Excellent Teamwork from Aplus Design Technologies in 2001, the Arnold O. Beckman Research Award from UIUC in 2007, and the NSF CAREER Award in 2008.